EXYNOS5: Change parent clock of FIMD to MPLL

With VPLL as source clock to FIMD,
Exynos DP Initializaton was failing sometimes with unstable clock.
Changing FIMD source to MPLL resolves this issue.

Signed-off-by: Ajay Kumar <[email protected]>
Acked-by: Simon Glass <[email protected]>
Acked-by: Donghwa Lee <[email protected]>
Signed-off-by: Minkyu Kang <[email protected]>

diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c
index ae6d7fe0d9b985a1f6bb92b2413910a035b1911a..abc327262a4eeacfe07455abad7cd959371298e4 100644 (file)
--- a/arch/arm/cpu/armv7/exynos/clock.c
+++ b/arch/arm/cpu/armv7/exynos/clock.c
@@ -741,7 +741,7 @@ void exynos5_set_lcd_clk(void)
         */
        cfg = readl(&clk->src_disp1_0);
        cfg &= ~(0xf);
-       cfg |= 0x8;
+       cfg |= 0x6;
        writel(cfg, &clk->src_disp1_0);
 
        /*